1. Field of Invention
The present invention relates to a power supply. More particularly, the present invention relates to a power supply supervisor and protection circuit.
2. Description of Related Art
At present, the power supply for a personal computer (PC) is required to have a power management function to save energy. FIG. 1 shows circuits of a power supply having a conventional power management function. The power supply has a transformer 10 that provides multiple output voltages V1, . . , Vn, such as a 3.3V, 5V, 12V, and xe2x88x9212V, for a variety of applications. A power supply supervisor 20 controls the output of the multiple output voltages V1, . . , Vn. The supervisor receives a control signal PSON from a CPU (central processor unit) of the computer to activate the output of the transformer 10. In other words, the control signal PSON is applied to turn off the power supply when the CPU enters into a sleep mode.
While the computer system is in the sleep mode, the transformer 15 provides a low stand-by power. When the computer is woken up, such as by triggering a keyboard of the computer system, the control signal PSON is set to the ON-state for activating the transformer 10 to output the multiple output voltages V1, . . , Vn. When the multiple output voltages V1, . . , Vn, reach the specified levels, a power good (PG) signal is sent by the supervisor 20 to the CPU, commanding the CPU to initiate input/output-accessing tasks.
The supervisor also includes protection functions, such as over-voltage protection and over current protection, for protecting the power supply and the circuit connected to the power supply. When abnormal situations occur, the supervisor 20 outputs a FAIL signal to inactivate the transformer 10 and stop output of the multiple output voltages V1, . . . , Vn, which avoids the permanent damage of the power supply and protect the connected circuits.
There are two types of protection circuits for the power supply: latch type and non-latch type. With regard to the latch type, the power supply remains in an off state even when the abnormal situation disappears. To restart the power, a reset procedure is necessary, for example, turning off the power supply to reset the latch and then turning on the power supply again.
However, the latch type power supply has the following defects. Reference is made to FIG. 1. When AC power is switched off, abnormal power supply situations may occur simultaneously, such as over-power, etc., which cause the supervisor 20 to disable the voltage outputs and latch the power supply to an off state. Since the power of supervisor 20 is supplied by the stand-by power through the transformer 15, the power supply is latched in the off state as long as the standby power exists. Since the power supply is latched in an off state, the transformer 10 is inactivated, therefore no energy is delivered from capacitor Cin to the transformer 10. The rest of the energy stored in capacitor Cin, providing the power for supervisor 20, can last several seconds. Accordingly, the power supply can only be switched on until the output of the standby power is exhausted. Otherwise, the power supply cannot be turned on because the latched status remains. When the computer is switched off and cannot be switched on again, the user may think that the power supply or the computer is damaged. To solve this problem, a dummy load is added to the output of the stand-by power to speed up the discharge of capacitor Cin. However, the dummy load increases power consumption and does not meet the power saving requirement.
Additionally, for stopping the access of flash-memory, disk driver, etc., a power-down-warning PG signal is required to inform the CPU that an AC that an AC power loss or AC power off occurred before the output voltages of the power supply are disabled. As shown in FIG. 2, the power-down-warning time TA is specified to meet the requirement. As shown in FIG. 3, a circuit for generating the power-down-warning PG signal is used according to the conventional method. FIG. 4 shows the voltage waveforms of FIG. 3. The pulse width of the PWM switching signal is controlled by the power supply for generating regulated outputs. The line voltage of the AC power determines the amplitude of the PWM switching signal. According to the turn ratio of the transformer 10, as shown in FIG. 3, the amplitude of the PWM switching signal 210 in the secondary is proportional to the line voltage in the primary. The conventional circuit shown in FIG. 3 is typically a rectification and filter circuit. If the resistance of the resistor 46 or the capacitance of the capacitor 46 is smaller, the discharge time will shorter, and the comparator 48 may incorrectly verify that a low line voltage is detected and generate an incorrect PG signal. If a larger resistance of the resistor 46 or a larger capacitance of the capacitor 46 is used, the discharge time is longer. The circuit of FIG. 3 may not generate a power-down-warning PG signal in time when AC power is lost or turned off.
The invention provides a power supply supervisor having a line voltage detector. The power supply supervisor comprises a peak detector, a time delay circuit and a logic circuit, which associate with the under-voltage detector, the over-voltage detector and the over-power detector to monitor the power supply.
The peak detector detects the line voltage by measuring the PWM switching signal in the secondary of the transformer and generating control signals. The under-voltage detector detects the levels of the output voltages. The over-voltage detector detects the levels of the output voltages that exceed the specified high level. The over-power detector monitors the output powers. The logic circuit couples to the peak detector, the under-voltage detector, the over-voltage detector. and the over-power detector, to generate a PG signal when the power supply outputs meet the specifications. The logic circuit outputs a FAIL signal to turn off the power supply when an abnormal situation such as over-voltage or over-power occurs. Furthermore. when AC power is lost or turned off, the logic circuit detects a low line voltage via the peak detector and generate a power-down-warning PG signal before the output voltages are disabled.
When an abnormal situation occurs before the low line voltage is detected, the logic circuit latches the power supply in an off state by latching the FAIL signal. If the abnormal situation occurs after the low line voltage is detected, the logic circuit turns off the power outputs by enabling the FAIL signal, but disables the latch function. In the mean time, a time delay circuit is applied to postpone the power off state, in which the time delay limits the duty cycle of power output and protects the power supply from over-stress damage.
The peak detector mentioned above may further comprises a maximum voltage detector for periodically sampling the amplitude of the PWM switching signal; a width detector for detecting the minimum pulse width of the PWM switching signal; a sample-comparator coupling to the maximum voltage detector and the width detector for immediately generating the control signal after the low line voltage is detected, thereby activates the power-down-warning PG signal.
Advantageously, the power supply supervisor having a line voltage detector of the present invention can provide a sufficient period of time for the power-down-warning PG signal before the output voltages of the power supply are disabled. In addition, the latch function of the power supply is disabled when the AC power is switched off. By this invention, the power supply can be switched on/off rapidly.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.